Silicon Verification Engineer 2

Role: Silicon Verification Engineer 2
Location: 100% remote

Duration: Till 9/30/2025 (Possible Extension : Yes)

Summary:
The main function of Silicon Verification Engineer is to be a part of the test-plan generation process, creating, testing, and implementing various verification plans.

Job Responsibilities:

• Define, document, and implement a UVM verification environment including agents and scoreboards
• Write test plans and implement them by developing tests, test generators, test benches, checkers, coverage, and other verification collateral
• Run tests on RTL and Gate Level Netlists, debug failures to root cause, and recommend fixes
• Support post-silicon verification activities of the products working with design and product teams
  

  Skills:

• Proficient in using Verilog and VMM/OVM/UVM
• Experience in pre and post silicon verification test flow and automated test benches
• Effective communication, collaboration, and teamwork skills
  

  Education/Experience:

• Bachelor's degree in electrical engineering, Computer Engineering, Computer Science, or related degree nice to have
• 2-4 years of relevant experience required.
  

  Purpose of the Team: The purpose of this team is IP verification to verify the design of high speed interface connecting different parts of an SOC chip.

• Key projects: This role will contribute to internal projects that cannot be shared at the moment. They will be working on Certus interfaces and high-speed serial interfaces (CRDAS) for several projects in AI and compute.
• Typical task breakdown and operating rhythm: The role will consist of meetings every day in the mornings which will go over agenda items like tasks and important actions. The remainder of their time is spent heads down focusing on assigned tasks (coding, data analysis, task management).
  

  Candidate Requirements

• Years of Experience Required: 2+, Ideally 3-6 overall years of experience in the field.
• Performance Indicators: Performance will be assessed based on completion of tasks within deadlines and responding to team questions and communicating issues with the team in a quick and timely manner.
  

  Top 3 Hard Skills Required + Years of Experience
  1. Minimum 2+years' experience with System Verilog and UVM.
  2. Minimum 2+years' experience with Mixed Signal Verification.
  3. Minimum 2+years' experience with Design Verification Methodology.

Dexian is a leading provider of staffing, IT, and workforce solutions with over 12,000 employees and 70 locations worldwide. As one of the largest IT staffing companies and the 2nd largest minority-owned staffing company in the U.S., Dexian was formed in 2023 through the merger of DISYS and Signature Consultants. Combining the best elements of its core companies, Dexian's platform connects talent, technology, and organizations to produce game-changing results that help everyone achieve their ambitions and goals.

Dexian's brands include Dexian DISYS, Dexian Signature Consultants, Dexian Government Solutions, Dexian Talent Development and Dexian IT Solutions. Visit https://dexian.com/ to learn more.

Dexian is an Equal Opportunity Employer that recruits and hires qualified candidates without regard to race, religion, sex, sexual orientation, gender identity, age, national origin, ancestry, citizenship, disability, or veteran status.