We use cookies. Find out more about it here. By continuing to browse this site you are agreeing to our use of cookies.
#alert
Back to search results

ASIC Design Verification Engineer

Cisco Systems, Inc.
United States, California, San Jose
170 W Tasman Dr (Show on map)
May 22, 2025

This application window is expected to close 6/25/25.


Meet the Team

The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. We design the networking hardware for Enterprises and Service Providers, the Public Sector, and Non-Profit Organizations across the world. Come join us and take part in shaping Cisco's ground-breaking solutions by designing, developing and testing some of the most complex ASICs being developed in the industry.

Your Impact

You will contribute to developing Cisco's revolutionary data center solutions by designing industry-leading complex chips, with full exposure to all aspects of our systems and applications, including silicon, hardware, software, telemetry, and security. Specific responsibilities include:

  • Architect and develop block, cluster, and top-level DV infrastructure from scratch, including maintaining and enhancing existing environments.
  • Create and execute test plans for design qualification at various levels, using a mix of constraint random and directed stimulus.
  • Ensure comprehensive verification coverage through code and functional coverage implementation and review.
  • Qualify RTL design quality with Gate Level Simulations and support emulation testing.
  • Collaborate with cross-functional teams to debug and optimize designs during post-silicon bring-up and manage the ASIC bring-up process.

Minimum Qualifications

  • Bachelor's Degree in EE, CE, or other related field.
  • 5+ years of related ASIC design verification experience.
  • Proficient in ASIC verification using UVM/System Verilog.
  • Proficient in verifying complex blocks, clusters and top level for ASIC.
  • Experience building test benches from scratch, hands on experience with System Verilog constraints, structures and classes.
  • Scripting experience with Perl and/or Python.

Preferred Qualifications

  • Master's Degree in EE or CE.
  • Experience with Forwarding logic/Parsers/P4.
  • Experience with Veloce/Palladium/Zebu/HAPS.
  • Formal verification (iev/vc formal) knowledge.
  • Domain experience on one or more protocols (PCIe, Ethernet, RDMA, TCP).

Why Cisco?

At Cisco, we're revolutionizing how data and infrastructure connect and protect organizations in the AI era - and beyond. We've been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Simply put - we power the future.

Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you'll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.

We are Cisco, and our power starts with you.

Applied = 0

(web-6787b74fd-l4cvn)